The purpose of an input protection circuit is to protect input gates, diffusions, metal lines, and other internal components of a chip from the potentially destructive effects of large electrostatic discharge (ESD) voltages applied to an input pad. Input protection circuits are typically formed along the periphery of semiconductor circuits, generally next to the input pads of the circuit. In most prior art devices, a separate input protection circuit is coupled to each input node, and some such schemes require an extra ion implant step for input/output transistors to enhance their performance when subjected to an ESD. Furthermore, the transistors in such input protection circuits typically must be large so as to be able to quickly absorb the current from an electrostatic discharge. As a result, such input protection circuits can occupy a sizeable amount of space, which increases the complexity and cost of the circuit.
The present invention provides a input protection circuit for CMOS devices that can be shared by many input/output nodes, thereby substantially reducing the complexity and amount of space occupied by input protection circuitry.